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Core Configuration
4.2 Bootstrap Program
The bootstrap program is factory-programmed in an internal 192-word by 24-bit bootstrap ROM
located in program memory space at locations $FF0000–$FF00BF. The bootstrap program can
load any program RAM segment from an external byte-wide EPROM, the SCI, or the host port.
The bootstrap program code is listed in Appendix A.
Upon exiting the Reset state, the DSP56311 samples the MOD[A–D] signal lines and loads their
values into OMR[MA–MD]. The mode input signals (MOD[A–D]) and the resulting MA, MB,
MC, and MD bits determine which bootstrap mode the DSP56311 enters (see Table 4-1 ).
Note:
To stop the bootstrap in any HI08 bootstrap mode, set the Host Flag 0 (HF0). The
loaded user program begins executing from the specified starting address.
You can invoke the bootstrap program options (except modes 0 and 8) at any time by setting the
MA, MB, MC, and MD bits in the OMR and jumping to the bootstrap program entry point,
$FF0000. Software can directly set the mode selection bits in the OMR. Bootstrap modes 0 and 8
are the normal DSP56311 functioning modes. Bootstrap modes 9, A, and C–F select different
specific bootstrap loading source devices. In these modes, the bootstrap program expects the
following data sequence when downloading the user program through an external port:
1.
2.
3.
Note:
Three bytes that specify the number of (24-bit) program words to be loaded
Three bytes that specify the (24-bit) start address where the user program loads in the
DSP56311 program memory
The user program (three bytes for each 24-bit program word)
The three bytes for each data sequence are loaded least significant byte first.
When the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
4.3 Central Processor Unit (CPU) Registers
There are two CPU registers that must be configured to initialize operation. The Status Register
(SR) selects various arithmetic processing protocols and contains several status reporting flag
bits. The Operating Mode Register (OMR) configures several system operating modes and
characteristics.
4.3.1
Status Register (SR)
The Status Register (SR) ( Figure 4-1 ) is a 24-bit register that indicates the current system state of
the processor and the results of previous arithmetic computations. The SR is pushed onto the
system stack when program looping is initialized or a JSR is performed, including long
interrupts. The SR consists of the following three special-purpose 8-bit control registers:
DSP56311 User’s Manual, Rev. 2
4-4
Freescale Semiconductor
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